An integrated circuit, in which a plurality of integrated circuit chips are laminated, is referred to as a three-dimensional integrated circuit. When the three-dimensional integrated circuit laminated with the chips, such as memory, is fabricated where a lot of non-defective chips can be obtained, a method of fabricating the three-dimensional integrated circuit by laminating a plurality of wafers is employed. A fabrication method of the three-dimensional integrated circuit like this is referred to as WtW (Wafer to Wafer). Throughput is high when the three-dimensional integrated circuit is fabricated by the WtW. When a defective chip exists in the respective wafers, however, the probability of obtaining a non-defective three-dimensional integrated circuit in the end, in other words, a yield becomes lower.
When the chips having various kinds of function are laminated to fabricate the three-dimensional integrated circuit, the non-defective chips, each being in a chip state, are laminated in the respective wafers, so as to fabricate the three-dimensional integrated circuit in which the plurality of chips, having different functions, are laminated. Such a fabrication method is referred to as CtC (Chip to Chip). Throughput is low when the three-dimensional integrated circuit is fabricated by the CtC. However, a yield becomes higher as the non-defective chips are used.
There is such a fabrication method of the three-dimensional integrated circuit that the chips are integrated three-dimensionally to the wafer (which is referred to as Chip to Wafer, CtW). However, significant problems of the CtW are low throughput and low alignment (also referred to as registration) accuracy.
In order to drastically increase the throughput and the alignment accuracy of an assembly, the present inventors have developed 3D integration technique using self-assembly of a multi-chip having surface tension of a liquid (multi chip-wafer 3D integration, which is referred to as SA-MCtW: Self Assembly based-Multi Chip to Wafer) (refer to Non Patent Literatures 1 to 4 and Patent Literature 1).
Patent Literature 1 is the invention filed by one of the present inventors. Patent Literature 1 discloses that the surface tension of an aqueous solution is used to position a chip onto a support substrate with high accuracy. The chip is temporarily fixed onto the support substrate by using absorption force of the aqueous solution. Patent Literature 1 discloses a “transfer method” in which a lot of the mounted chips are replaced onto a target substrate.
Electrostatic chucking is well known as a processing method of wafers. Recently, a processing system of a multipurpose and thin wafer, by using an electrostatic wafer carrier, has been reported by C. Landesberger, P. Ramm, K. Bock et al. (refer to Non Patent Literature 5).